bingshuo/hololake-system-architecture
Watch
1
0
Fork
You've already forked hololake-system-architecture
 0
Code Issues Pull requests 1 Projects Releases Packages Wiki Activity

feat(tcs): add stage2 mother-brain and desktop ABI

Browse source
This commit is contained in:
冰朔 2026-08-23 23:18:11 +08:00
commit d5c87e3768
59 changed files with 5788 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

4
README.md
View file

@ -4,4 +4,6 @@ This branch starts the HoloLake language mother-model line under `ICE-CH-ZC001`
Canonical source is TCS only. Generated GIR, bilingual human projections, runtime readbacks and receipts are evidence layers, not replacement canon. Legacy product sources live in the separate mobile-drive reference isolation zone and are not part of this line.
The first accepted slice preserves a direct-language source envelope, extracts a three-node thought-transition microchain, compiles it with the Stage-1 TCS compiler and executes a bounded replay receipt through the current TCS GIR runtime. Desktop object/action operations remain explicitly unimplemented until their TCS-native ABI, registry and runtime path exist.
The first accepted slice preserves a direct-language source envelope, extracts two three-node thought-transition microchains, compiles them and executes bounded replay receipts through the current TCS GIR runtime.
Stage two adds the TCS-authored `TCS-COMPILER-STAGE2-LPM-DESKTOP-0001`, a fixed-point operation registry, a P2 mother-brain state transition program, a five-action shared-desktop test-object graph, and two complete Module ABI packages at `VERIFIED`. Compilation admission is proven; native LPM and generic multi-action runtime dispatch are still absent and fail closed with `TCS-E2101`. The modules are not installed, mounted, active, executed or accepted.